WO2012176370A1 - シリコンウェーハ及びその製造方法 - Google Patents
シリコンウェーハ及びその製造方法 Download PDFInfo
- Publication number
- WO2012176370A1 WO2012176370A1 PCT/JP2012/003121 JP2012003121W WO2012176370A1 WO 2012176370 A1 WO2012176370 A1 WO 2012176370A1 JP 2012003121 W JP2012003121 W JP 2012003121W WO 2012176370 A1 WO2012176370 A1 WO 2012176370A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon wafer
- wafer
- lpd
- mirror
- polished
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 182
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 181
- 239000010703 silicon Substances 0.000 title claims abstract description 181
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 57
- 238000010438 heat treatment Methods 0.000 claims abstract description 99
- 238000005498 polishing Methods 0.000 claims abstract description 78
- 239000013078 crystal Substances 0.000 claims abstract description 71
- 235000012431 wafers Nutrition 0.000 claims description 255
- 239000002245 particle Substances 0.000 claims description 31
- 230000007547 defect Effects 0.000 abstract description 54
- 230000002950 deficient Effects 0.000 abstract description 15
- 238000007689 inspection Methods 0.000 abstract description 15
- 238000002360 preparation method Methods 0.000 abstract description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 35
- 239000010949 copper Substances 0.000 description 23
- 239000004065 semiconductor Substances 0.000 description 18
- 238000007517 polishing process Methods 0.000 description 17
- 238000001514 detection method Methods 0.000 description 16
- 239000012535 impurity Substances 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 11
- 238000011109 contamination Methods 0.000 description 11
- 238000005259 measurement Methods 0.000 description 11
- 238000012790 confirmation Methods 0.000 description 10
- 229910052759 nickel Inorganic materials 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000012299 nitrogen atmosphere Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001095 inductively coupled plasma mass spectrometry Methods 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000004931 aggregating effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000013441 quality evaluation Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005211 surface analysis Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/20—Controlling or regulating
- C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/14—Heating of the melt or the crystallised materials
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/20—Controlling or regulating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
Definitions
- the present invention relates to a silicon wafer in which LPD (Light Point Defect) on the surface is reduced to the limit, and a method for manufacturing the same.
- LPD Light Point Defect
- a silicon wafer used as a material for manufacturing a semiconductor device is sliced from a silicon single crystal grown by a Czochralski (CZ) method, in particular, a Magnetic field applied Czochralski (MCZ) method for producing a crystal while applying a magnetic field.
- CZ Czochralski
- MCZ Magnetic field applied Czochralski
- a polished substrate is used.
- a laser type particle counter is used for the quality evaluation of the silicon wafer surface, and with the miniaturization of the element design rule, the particle detection size is 45 nm or less. For this reason, it is possible to prevent minute defects caused by processing in the mirror polishing process of the wafer surface, and minute foreign matter and impurities in the subsequent wafer cleaning.
- Non-patent Document 1 a COP (Non-patent Document 1) exists as a crystal defect on the silicon wafer surface and a concave depression is formed on the wafer surface, it is measured as LPD by a laser particle counter. That is, an object that is not an actual foreign object may be detected as a particle. It has been reported that these crystal defects are formed according to the temperature gradient (G) and the growth rate (V) during crystal growth (Non-patent Document 2). Further, a manufacturing method in which these G and V are controlled, for example, Patent Document 1, reports a method for controlling the formation of crystal defects by reducing the growth rate of a silicon single crystal.
- the COP is substantially increased by pulling at a speed (V) not exceeding the maximum pulling speed of the single crystal that is substantially proportional to the temperature gradient (G) of the boundary region in the solid phase / liquid phase of the silicon single crystal. It has been reported that no defect-free crystals are obtained.
- JP-A-6-56588 Japanese Patent Laid-Open No. 7-257991 WO2010 / 140671A1 publication JP-A-9-64052 Jpn. J. Appl. Phys. , 29 (1990), L1947-L1949 Japan Society for Crystal Growth vol. 25 No. 5, (1998) Jpn. J. Appl. Phys. , 31 (1990), L1947 Latest silicon devices and crystal technology, Realize, published on December 26, 2005 171 Analytical Handbook for ULSI Manufacturing, Realize, published on July 29, 1994, p. 115
- micro LPD formation causes are reported to be caused by heavy metal contamination on the wafer.
- typical heavy metal contamination is contamination by copper (Cu), which occurs in a polishing process, a cleaning process, a heat treatment process, or the like for manufacturing a wafer.
- Copper contamination is likely to occur because the diffusion rate of copper is faster than other heavy metals.
- Patent Document 4 For cleaning the surface of the wafer, for example, HF solution, HF / H 2 O 2 solution, HCl solution, HCl / H 2 O 2 solution, HCl / HF solution, SC1 solution, H 2 SO 4 / H 2 are used.
- An O 2 solution or the like is used. It is disclosed that heavy metals are reduced by these treatments.
- the present invention has been made in view of the above problems, and is a method for manufacturing a silicon wafer from a defect-free silicon single crystal grown by the CZ method, in which a minute LPD is reduced to the limit, and an inspection process and shipping.
- An object is to provide a silicon wafer.
- a silicon wafer is produced from a defect-free silicon single crystal grown by the CZ method, After preparing a silicon wafer sliced from the defect-free silicon single crystal and mirror-polished, A heat treatment step of heat-treating the mirror-polished silicon wafer at a temperature of 500 ° C. or more and 600 ° C. or less for 4 hours or more and 6 hours or less; There is provided a method for producing a silicon wafer, comprising performing a re-polishing step of re-polishing the silicon wafer after the heat treatment step so that the polishing amount becomes 1.5 ⁇ m or more.
- LPD can be reduced by removing them by a re-polishing step. Therefore, even if defect-free silicon single crystals are contaminated with heavy metals during growth, LPD is reduced to the limit, and silicon wafers that can be manufactured with high yield can be produced with low yield of defective products in the inspection process and shipping stage. Become a method.
- the silicon wafer manufacturing method of the present invention can reduce micro LPDs having a size of about 45 nm, which could not be removed in the past, to the limit regardless of the type of heavy metal that causes LPD. is there.
- the silicon wafer having 10 / wafer or less LPD having a particle size of 37 nm to 120 nm, which is detected by a particle counter, can be manufactured.
- a silicon wafer having a diameter of 300 mm or more as the sliced and mirror-polished silicon wafer.
- a heat treatment step and a re-polishing step can be performed to produce a silicon wafer in which minute LPD is reliably reduced.
- a silicon wafer that has been subjected to a heat treatment of a mirror-polished silicon wafer and re-polished, wherein the number of LPDs with a particle size of 37 nm to 120 nm detected by a particle counter is 10 / wafer or less I will provide a.
- the defect generation rate is low in the inspection process and the shipping stage, and the wafer for process confirmation used in the semiconductor element manufacturing process and the highly integrated semiconductor element It becomes a silicon wafer suitable for manufacturing.
- the diameter of the silicon wafer is preferably 300 mm or more.
- a large-diameter wafer used for such a state-of-the-art application is a process confirmation wafer used in a more advanced semiconductor element manufacturing process and a silicon wafer that is optimal for manufacturing highly integrated semiconductor elements.
- the heat treatment process is performed to collect heavy metals that cause LPD in the vicinity of the surface of the silicon wafer after mirror polishing, and this is performed by the re-polishing process. Since the LPD can be reduced by removing the defect, even if the defect-free silicon single crystal is contaminated with heavy metals during the growth, the LPD is reduced to the limit, and the defective product generation rate is increased in the inspection process and the shipping stage.
- This is a silicon wafer manufacturing method capable of manufacturing a low silicon wafer with a high yield.
- the silicon wafer of the present invention is a high-quality silicon wafer in which LPD is reduced to the limit when measurement is performed with a particle counter, and a process confirmation wafer used in a semiconductor element manufacturing process, It is possible to provide an optimal silicon wafer for manufacturing a highly integrated semiconductor device.
- the present invention is not limited thereto.
- the detection size can be set by the particle counter.
- the problem is that LPDs derived from heavy metals are detected at a high density, and these LPDs cannot be easily removed. Therefore, development of a silicon wafer manufacturing method capable of reducing the heavy metal-derived LPD to the limit and development of a silicon wafer having the LPD reduced to the limit have been desired.
- the inventors of the present invention have made extensive studies as described above and found that the cause of LPD formation of a silicon wafer sliced from a defect-free silicon single crystal is a heavy metal, particularly Cu and Ni, mixed in a trace amount during pulling. . These aggregate and grow to a minute size due to the thermal history during the production of the silicon single crystal.
- the present inventors selectively etch in the case of Cu to form minute pits, and in the case of Ni, the etching slows down to form minute hillocks (convex shape). And found that these shapes are detected as LPD by a laser type particle counter.
- FIG. 1A LPD was detected even though the silicon wafer was cut from a defect-free silicon single crystal. Therefore, in order to investigate the actual state of the detected LPD, the surface of the mirror-polished wafer I was observed using a scanning electron microscope (SEM).
- FIG. 1B shows six observation results of typical defect shapes observed. As shown in FIG. 1B, the observed LPD shape was found to be a pit-like defect.
- FIG. 2A shows the detected LPD map in the wafer surface
- FIG. 2B shows the observation result of the surface of the mirror-polished wafer II by SEM.
- FIG. 2A it was confirmed that LPD was generated on the surface of the mirror polished wafer II.
- FIG. 2B it was found that the shape of the LPD detected at this time was a convex hillock. From this difference in shape, it was found that the cause of LPD formation in the mirror-polished wafer II is different from that in the mirror-polished wafer I.
- FIG. 4 The observation result by SEM of a typical PID formed on the mirror-polished wafer IV is shown in FIG. As shown in FIG. 4, the shape of the PID was an elongated line. This clearly shows that the defects of the mirror polished wafers I and II are different from those of the PID.
- Example 5 Re-polishing of mirror-polished wafer I
- the LPD formed on the mirror-polished wafer I of Experimental Example 1 is clearly different from the cavity defect (COP) shown in Experimental Example 3 from detailed shape observation by SEM.
- polishing process shown in Experimental example 4 was shown.
- the mirror-polished wafer I was re-polished to obtain a mirror-polished wafer V, and the LPD of the mirror-polished wafer V was measured again.
- the re-polishing was performed with a polishing amount of 1.5 ⁇ m.
- the LPD map after re-polishing is shown in FIG.
- the mirror-polished wafer V has the same irregular pit-like defects as those of the mirror-polished wafer I.
- the pit-like defects are caused by the polishing process. It was confirmed that it was not a thing.
- Example 6 Repolishing of mirror polished wafer II
- the LPD formed on the mirror-polished wafer II in Experimental Example 2 is clearly different from the cavity defect (COP) shown in Experimental Example 3 from detailed shape observation by SEM. Moreover, the defect shape different from PID by the influence of the grinding
- the mirror-polished wafer II was re-polished to give a mirror-polished wafer VI, and the LPD of the mirror-polished wafer VI was measured again. .
- the re-polishing was performed with a polishing amount of 1.5 ⁇ m.
- FIG. 6A shows the LPD map after re-polishing
- FIG. 6A shows the LPD map after re-polishing
- FIGS. 6 (a) and 6 (b) show the confirmation result of the defect shape by SEM.
- the mirror-polished wafer VI had the same irregular convex hillocks as the mirror-polished wafer II. From this, it was confirmed that the PLD defect of the mirror polished wafer II was not caused by the polishing process.
- the heat treatment atmosphere was a nitrogen atmosphere
- the heat treatment temperature was 1000 ° C.
- the time was 60 minutes.
- Table 1 shows the results when impurities were measured again on the heat-treated mirror-polished wafer I by the WSA method and compared with a normal product. Among various heavy metal impurities, Cu was detected at about one digit higher concentration. In Table 1, ND indicates that it is below the detection limit.
- the silicon wafer shown in Experimental Example 2 was heat-treated in a nitrogen atmosphere at 500 ° C. for 6 hours. Thereafter, the surface was repolished by 1.5 ⁇ m to prepare a mirror polished wafer VIII, and LPD measurement was performed with a particle counter.
- the LPD measurement result is shown in FIG. 8A, and the defect observation result by SEM is shown in FIG. 8B.
- LPD was significantly reduced compared to FIG. 2 (a).
- the hillock-like defect was lose
- the LPD was sufficiently reduced at the heat treatment temperature of 500 ° C., but the number of LPDs was 102 / wafer at the heat treatment temperature of 400 ° C. As a result, the effect of reducing the LPD was insufficient. This is presumably because the diffusion rate of Ni in the silicon wafer was relatively slow, and the heat treatment temperature of less than 500 ° C. did not sufficiently move to the silicon wafer surface.
- the LPD was 6 / wafer sufficiently low after the heat treatment and re-polishing. This is thought to be because the diffusion rate of Cu in the silicon wafer is very fast, easily moves to the surface of the silicon wafer, and can be removed by re-polishing.
- the heat treatment temperature is set to 500 ° C. or higher in order to avoid re-heat treatment and re-polishing.
- the heat processing temperature shall be 600 degrees C or less.
- Example 10 LPD reduction effect when heat treatment time is changed
- the heat treatment temperature was 500 ° C.
- the re-polishing amount was 1.5 ⁇ m
- the heat treatment time was 4 levels of 3 hours, 4 hours, 6 hours, and 8 hours.
- Table 4 shows the measurement results of the number of LPDs of each mirror-polished wafer after the heat treatment step and the re-polishing step.
- the LPD was sufficiently reduced in the heat treatment time of 4 hours or more and up to 8 hours, but the number of LPDs was 68 under the condition of the heat treatment time of 3 hours. / Wafer and LPD reduction effect was insufficient. Further, in the mirror polished wafer I of Experimental Example 1, even when the heat treatment time was 3 hours, the LPD was a low value of 4 pieces / wafer.
- the heat treatment time is set to 4 hours or longer so that re-heat treatment and re-polishing are not necessary.
- the heat treatment time exceeds 6 hours, the process time becomes long and the production efficiency decreases.
- the heat treatment time is longer than 6 hours, it greatly affects the precipitation characteristics of interstitial oxygen in the silicon wafer. That is, it adversely affects BMD (Bulk Micro Defect) characteristics. If BMD is formed in the vicinity of the wafer surface due to excessive oxygen precipitation, it may cause a leak in the semiconductor element formation process thereafter. Therefore, in the present invention, the heat treatment time is set to 6 hours or less in order to avoid these problems.
- the re-polishing amount is set to 1.5 ⁇ m or more so as not to be additionally re-polished.
- the heavy metal is gathered near the surface of the silicon wafer after mirror polishing without reducing the yield, and the LPD is reduced by removing it by the repolishing process.
- a method can reduce microLPD having a size of about 45 nm, which could not be removed in the past, due to heavy metal contamination during crystal growth that causes LPD.
- the present inventors have found that even if a defect-free silicon single crystal is contaminated with heavy metals at the time of growth, LPD is reduced to the limit, and a silicon wafer with a low defective product generation rate in the inspection process and the shipping stage is obtained.
- the present inventors have found a method of manufacturing a silicon wafer that can be manufactured with a high yield. The present invention will be described below.
- the present invention is a method for producing a silicon wafer from a defect-free silicon single crystal grown by the CZ method, After preparing a silicon wafer sliced from the defect-free silicon single crystal and mirror-polished, A heat treatment step of heat-treating the mirror-polished silicon wafer at a temperature of 500 ° C. or more and 600 ° C. or less for 4 hours or more and 6 hours or less;
- the silicon wafer manufacturing method is characterized by performing a re-polishing step of re-polishing the silicon wafer after the heat treatment step so that the polishing amount becomes 1.5 ⁇ m or more.
- the defect-free silicon single crystal can be grown by the CZ method, particularly by the MCZ method to which a magnetic field is applied.
- the defect-free silicon single crystal means a silicon single crystal composed of the entire N-region having no void type defect, OSF, or dislocation cluster.
- a silicon single crystal has an excess of interstitial silicon point defects caused by the presence of excess silicon atoms in the V-region where there are excessive vacancy-type point defects caused by a shortage of silicon atoms.
- grow-in defects FPD, LSTD, COP, etc.
- the concentration of these two point defects is determined from the relationship between the crystal pulling rate (growth rate) V in the CZ method and the temperature gradient G in the vicinity of the solid-liquid interface in the crystal. Since the parameter V / G determines the total concentration of point defects, a crystal with an N-region extending across the entire lateral surface can be manufactured by adjusting the pulling speed so that V / G becomes a predetermined value. It is known that the crystal of the entire N-region can be expanded in the length direction by maintaining the pulling speed when the N-region spreads horizontally.
- the defect-free silicon single crystal in the present invention is a silicon single crystal of the entire N-region grown in this way.
- a defect-free silicon single crystal is sliced, and the sliced wafer is mirror-polished to prepare a silicon wafer.
- This wafer processing step is not particularly limited, and any of the generally performed steps can be applied. In particular, after slicing, chamfering, lapping, etching, and mirror polishing are typical, but other processes may be used. Although not particularly limited, it is preferable to prepare a silicon wafer having a diameter of 300 mm or more as a sliced and mirror-polished silicon wafer. Even for a large-diameter wafer used for such a state-of-the-art product, a high-quality silicon wafer with reduced LPD can be produced by performing the heat treatment step and the re-polishing step of the present invention.
- the mirror-polished silicon wafer is heat-treated at a temperature of 500 ° C. or more and 600 ° C. or less for 4 hours or more and 6 hours or less.
- a relatively low temperature heat treatment process utilizing the high diffusion rate of heavy metals, particularly Cu and Ni, in the silicon single crystal, Cu and Ni are brought into the vicinity of the surface of the silicon wafer after mirror polishing. Can be assembled.
- the heat treatment furnace to be used is not particularly limited, and it is efficient if a vertical or horizontal batch furnace is used.
- the heat treatment temperature is set to 500 ° C. or higher so that no additional heat treatment is required in consideration of the contamination state of which heavy metal is contaminated, and the heat from the wafer support part during the heat treatment.
- the temperature is set to 600 ° C. or lower.
- the heat treatment time is set to 4 hours or more so that no additional heat treatment is required, and 6 hours so as not to adversely affect the production efficiency and BMD characteristics. The following.
- the silicon wafer after the heat treatment step is re-polished so that the polishing amount becomes 1.5 ⁇ m or more.
- the polishing amount is set to 1.5 ⁇ m or more so that additional re-polishing is not necessary.
- the polishing method can be any polishing method generally used for silicon wafers, and is not particularly limited. For example, CMP using colloidal silica as an abrasive can be performed.
- the LPD is reduced to the limit, and in the inspection process and the shipping stage when manufacturing the silicon wafer The defective product generation rate is reduced, and a silicon wafer manufacturing method with a good yield is obtained.
- the silicon wafer having 10 / wafer or less LPD having a particle size of 37 nm to 120 nm detected by a particle counter can be produced.
- LPD is reduced, a silicon wafer having a lower defect generation rate in the inspection process and the shipping stage can be manufactured with a high yield.
- the silicon wafer produced by the silicon wafer manufacturing method has an LPD reduced to the utmost even when a defect-free silicon single crystal is contaminated with heavy metal during growth, and the defective product generation rate in the inspection process and the shipping stage.
- the process confirmation wafer used in the most advanced semiconductor element manufacturing process and a silicon wafer optimal for manufacturing highly integrated semiconductor elements are obtained.
- a silicon wafer obtained by heat-treating a mirror-polished silicon wafer and re-polished wherein the number of LPDs having a particle size of 37 nm to 120 nm detected by a particle counter is 10 / wafer or less.
- a wafer can be obtained.
- the LPD is reduced to the limit, the defective product generation rate is low in the inspection process and the shipping stage, and the process confirmation wafer used in the most advanced semiconductor element manufacturing process
- the silicon wafer is suitable for manufacturing highly integrated semiconductor devices.
- the diameter of the said silicon wafer is 300 mm or more.
- Such a state-of-the-art large-diameter wafer is an optimal silicon wafer for manufacturing a process confirmation wafer used in a semiconductor element manufacturing process or a highly integrated semiconductor element.
- Example 1 A quartz crucible with a diameter of 810 mm is filled with 410 kg of polycrystalline silicon, and a defect-free silicon single crystal with a diameter of 300 mm is grown by controlling the temperature gradient (G) and growth rate (V) of the solid / liquid layer boundary region of silicon. did. At this time, boron was doped so that the specific resistance was 10 ⁇ ⁇ cm, and the crystal axis orientation was ⁇ 100>.
- the defect-free silicon single crystal was sliced, chamfered, lapped, etched, and mirror-polished to produce a mirror-polished wafer. This mirror-polished wafer was heat-treated in a nitrogen atmosphere at a heat treatment temperature of 500 ° C.
- Example 2 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 600 ° C. and a heat treatment time of 4 hours, and re-polished to a re-polishing amount of 1.5 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 3 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 500 ° C. and a heat treatment time of 6 hours, and re-polished to a re-polishing amount of 1.5 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 4 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 500 ° C. and a heat treatment time of 4 hours, and re-polished to a re-polishing amount of 2.0 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 1 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 400 ° C. and a heat treatment time of 4 hours, and re-polished to a re-polishing amount of 1.5 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 2 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 700 ° C. and a heat treatment time of 4 hours, and re-polished to a re-polishing amount of 1.5 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 3 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 500 ° C. and a heat treatment time of 3 hours, and re-polished to a re-polishing amount of 1.5 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 4 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 500 ° C. and a heat treatment time of 8 hours, and re-polished to a re-polishing amount of 1.5 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Example 5 A mirror-polished wafer produced in the same manner as in Example 1 was heat-treated at a heat treatment temperature of 500 ° C. and a heat treatment time of 4 hours, and re-polished to a re-polishing amount of 1.0 ⁇ m to produce a silicon wafer.
- Table 6 shows the detection results of LPD.
- Examples 1 to 4 of the present invention heat treatment at a relatively low temperature of 500 to 600 ° C. for 4 to 6 hours is performed by utilizing the high diffusion rate of heavy metals, particularly Cu and Ni, in a silicon single crystal.
- heavy metals can be gathered in the vicinity of the surface of the silicon wafer after mirror polishing, and further, by removing this by a re-polishing process with a polishing amount of 1.5 ⁇ m or more, LPD can be reduced. It was shown that it can be done.
- the silicon wafer of the present invention is used, the LPD is reduced to the limit, the defective product generation rate is low in the inspection process and the shipping stage, the wafer for process confirmation used in the state-of-the-art semiconductor device manufacturing process, and a highly integrated wafer It becomes a silicon wafer most suitable for the manufacture of semiconductor elements.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
Abstract
Description
前記無欠陥シリコン単結晶からスライスされ、鏡面研磨されたシリコンウェーハを準備した後に、
前記鏡面研磨されたシリコンウェーハを、500℃以上600℃以下の温度で、4時間以上6時間以下の時間で熱処理する熱処理工程と、
前記熱処理工程後のシリコンウェーハを、研磨量が1.5μm以上となるように再研磨する再研磨工程とを行うことを特徴とするシリコンウェーハの製造方法を提供する。
まず、LPDの発生原因を突き止めるために、直径810mmの石英ルツボに多結晶シリコンを410kg充填し、溶融後に特許文献2に開示されたようにシリコンの固層/液層境界領域の温度勾配(G)と成長速度(V)を制御することにより直径300mmの無欠陥シリコン単結晶を育成した。この際、比抵抗は10Ω・cmとなるようにボロンをドープし、結晶軸方位は<100>とした。この無欠陥シリコン単結晶に工業的に一般に適用されるスライス、ラッピング、エッチング、鏡面研磨等を施し鏡面研磨ウェーハIを作製した。この鏡面研磨ウェーハIをパーティクルカウンター(KLA Tencor社 モデル名=SP2 検出粒径サイズは0.037μm以上)にて測定した。ウェーハ面内のLPDマップの検出結果を図1(a)に示した。
次に、前記実験例1と同様にして異なる石英ルツボで作製した無欠陥シリコン単結晶から鏡面研磨ウェーハIIを作製し、LPDを調査した。検出されたウェーハ面内のLPDマップを図2(a)に示し、鏡面研磨ウェーハIIの表面のSEMによる観察結果を図2(b)に示した。図2(a)に示されるように、鏡面研磨ウェーハIIの表面にLPDが発生していることが確認できた。また、図2(b)に示されるように、この際に検出されたLPDの形状は凸状のヒロックであることがわかった。この形状の違いより鏡面研磨ウェーハIIのLPDの形成原因は鏡面研磨ウェーハIとは異なる事がわかった。
結晶欠陥はLPDとして検出されることが知られている。COP(Crystal Originated Particle)は八面体の空洞欠陥として検出されることが報告されている(非特許文献3)。鏡面研磨ウェーハI及びIIにおいて検出された欠陥形状がCOPと関係しているか確認するために、COPが発生するように結晶成長速度を2倍にして直径300mmのシリコン単結晶を育成した。他の育成条件は実験例1と同一の条件とした。このシリコン単結晶からスライスされ、鏡面研磨された鏡面研磨ウェーハIIIのLPDの形状をSEMにより観察した結果を図3に示した。図3に示されるように、COP起因の欠陥は、一辺が[110]方向に囲まれた2つの欠陥が一部重なった、いわゆるツインピットと呼ばれる空洞欠陥であった。これにより明らかに鏡面研磨ウェーハI及びIIの欠陥はCOPとは異なることがわかった。
LPDは鏡面研磨工程によっても形成されることが知られている。特に鏡面研磨工程によって形成される欠陥はPID(Polished Induced Defect)と呼ばれ、無欠陥シリコンウェーハで顕著に検出される(非特許文献4)。また、特許文献3ではPIDが鏡面研磨の際の残渣により形成されることが開示されている。鏡面研磨ウェーハI及びIIで検出された欠陥形状がPIDと関係しているのか調査するために、あらかじめ実験例1及び実験例2に示すような無欠陥シリコン単結晶からスライスしたウェーハを選定し、一般的に行われている鏡面研磨工程中に故意にNiおよびCuを混入させて研磨し、鏡面研磨ウェーハIVを得た。鏡面研磨ウェーハIVに形成された代表的なPIDのSEMによる観察結果を図4に示した。図4に示されるように、PIDの形状は細長い線状であった。これより明らかに鏡面研磨ウェーハI及びIIの欠陥はPIDとは異なることがわかった。
実験例1の鏡面研磨ウェーハIに形成されたLPDは、SEMによる詳細な形状観察より、実験例3で示した空洞欠陥(COP)とは明白に異なる。また、実験例4で示した研磨工程の影響によるPIDとも異なる欠陥形状を示した。更に、研磨工程によるLPDへの影響を再度確認するために、鏡面研磨ウェーハIを再研磨して鏡面研磨ウェーハVとし、鏡面研磨ウェーハVのLPDの再測定を行った。再研磨は研磨量1.5μmとした。再研磨後のLPDマップを図5(a)に示し、SEMによるLPDの形状の確認結果を図5(b)に示した。図5(a)、図5(b)に示されるように、鏡面研磨ウェーハVには鏡面研磨ウェーハIと同一の不定形のピット状の欠陥が見られ、このピット状の欠陥は研磨工程によるものではないことが確認できた。
実験例2の鏡面研磨ウェーハIIに形成されたLPDは、SEMによる詳細な形状観察より、実験例3で示した空洞欠陥(COP)とは明白に異なる。また、実験例4で示した研磨工程の影響によるPIDとも異なる欠陥形状を示した。実験例5と同様に、更に、研磨工程によるLPDへの影響を再度確認するために、鏡面研磨ウェーハIIを再研磨して鏡面研磨ウェーハVIとし、鏡面研磨ウェーハVIのLPDの再測定を行った。再研磨は研磨量1.5μmとした。再研磨後のLPDマップを図6(a)に示し、SEMによる欠陥形状の確認結果を図6(b)に示した。図6(a)、図6(b)に示されるように、鏡面研磨ウェーハVIには鏡面研磨ウェーハIIと同一の不定形の凸状のヒロックが見られた。これより鏡面研磨ウェーハIIのPLD欠陥は研磨工程によるものではないことが確認できた。
再研磨によっても同一の欠陥形状を示したことからピット状のLPDは研磨工程に由来する欠陥ではないことが確認できた。欠陥の形成原因を更に調査するために実験例1の鏡面研磨ウェーハIについて不純物測定を行った。測定法は、ウェーハ表面の不純物測定において一般的に用いられているWSA(Wafer Surface Analysis)(非特許文献5)法であり、不純物を含む回収液を誘導結合プラズマ質量分析法(ICP-MS)にて検出した。実験例1の鏡面研磨ウェーハIを分析した結果、不純物は検出限界以下であった。そのため、バルク不純物をウェーハ表面に移動させる目的で熱処理を行った。熱処理雰囲気は窒素雰囲気中で、熱処理温度は1000℃、時間は60分とした。熱処理した鏡面研磨ウェーハIを再度WSA法にて不純物測定を行って、正常品と比べたときの結果を表1に示した。各種の重金属不純物の中でCuが約1桁高濃度に検出された。表1中NDは検出限界以下であることを示す。
実験例2の鏡面研磨ウェーハIIでSEMにより観察できた欠陥は、COP、PID及び実験例1の鏡面研磨ウェーハIのLPDとはまったく異なる形状であった。そこで、前記と同様に鏡面研磨ウェーハIIを1000℃、60分で熱処理した後、WSA法による不純物分析を実施した。分析結果を表2に示した。表2より各種の重金属不純物の中でNi濃度が高いことがわかった。表2中NDは検出限界以下であることを示す。
実験例1の鏡面研磨ウェーハIのLPDは、COP、PIDが原因ではないことが確認できた。しかしパーティクルカウンターで測定した場合には微小なピット状の欠陥が形成され、このウェーハはCu濃度が通常より高いものであった。以上の結果より、ピット状の欠陥はシリコン単結晶育成時に微量に混入したCuが原因であり、結晶育成中の熱履歴により凝集し欠陥を形成したことが考えられる。
同様に、実験例2の鏡面研磨ウェーハIIのLPDも、COP、PIDが原因ではないことが確認できた。しかしパーティクルカウンターで測定した場合には微小なヒロック状の欠陥が形成され、このウェーハはNi濃度が通常より高いものであった。以上の結果より、ヒロック状の欠陥はシリコン単結晶育成時に微量に混入したNiが原因であり、結晶育成中の熱履歴により凝集し欠陥を形成したことが考えられる。
実験例7及び実験例8より、シリコン単結晶育成中に微量に混入した重金属不純物(特にCu、Ni)を起因とするLPDは、ウェーハを熱処理し、再研磨することにより低減できることが確認できた。そこで、実験例1及び実験例2の鏡面研磨ウェーハを用い、熱処理温度を変化させた場合のLPD低減効果を確認した。熱処理時間は4時間、再研磨量は1.5μmとし、熱処理温度を400℃、500℃、600℃、700℃の4水準とした。熱処理工程及び再研磨工程後の各鏡面研磨ウェーハのLPDの個数の測定結果を表3に示した。
次に、実験例1及び実験例2の鏡面研磨ウェーハを用いて、熱処理時間を変化させた場合のLPD低減効果を確認した。熱処理温度は500℃、再研磨量は1.5μmとし、熱処理時間を3時間、4時間、6時間、8時間の4水準とした。熱処理工程及び再研磨工程後の各鏡面研磨ウェーハのLPDの個数の測定結果を表4に示した。表4に示されるように、実験例2の鏡面研磨ウェーハIIでは4時間以上、8時間までの熱処理時間にてLPDが十分低減したが、3時間の熱処理時間の条件ではLPDの個数が68個/waferとLPD低減効果が不十分となる結果であった。また、実験例1の鏡面研磨ウェーハIでは熱処理時間が3時間であっても、LPDは4個/waferと低い値であった。
最後に、実験例1及び実験例2の鏡面研磨ウェーハを用いて、再研磨量を変化させた場合のLPD低減効果を確認した。熱処理温度は500℃、熱処理時間は4時間とし、再研磨量を0.5μm、1.0μm、1.5μm、2.0μmの4水準とした。熱処理工程及び再研磨工程後の各鏡面研磨ウェーハのLPDの個数の測定結果を表5に示した。表5に示されるように、再研磨量が1.5μm以上の場合には実験例1及び実験例2の鏡面研磨ウェーハのLPDが十分に低減したが、再研磨量が1.0μmの場合には実験例2の鏡面研磨ウェーハのLPDは低減しなかった。したがって、本発明では、追加して再研磨する必要のないよう再研磨量を1.5μm以上とする。
前記無欠陥シリコン単結晶からスライスされ、鏡面研磨されたシリコンウェーハを準備した後に、
前記鏡面研磨されたシリコンウェーハを、500℃以上600℃以下の温度で、4時間以上6時間以下の時間で熱処理する熱処理工程と、
前記熱処理工程後のシリコンウェーハを、研磨量が1.5μm以上となるように再研磨する再研磨工程とを行うことを特徴とするシリコンウェーハの製造方法である。
本発明において無欠陥シリコン単結晶はCZ法により育成し、特に磁場を印加したMCZ法により育成することができる。また、本発明において無欠陥シリコン単結晶とは、ボイド型欠陥もOSFも転位クラスターもない全面N-領域からなるシリコン単結晶をいう。一般的にシリコン単結晶には、シリコン原子の不足から発生する空孔型の点欠陥が過剰にあるV-領域、シリコン原子が余分に存在することにより発生する格子間型シリコン点欠陥が過剰にあるI-領域、そしてV-領域とI-領域の間に、原子の不足や余分が無い(少ない)N-領域が存在する。そして、VやIが過飽和な状態の時に、グローンイン欠陥(FPD、LSTD、COP等)が発生する。
本発明では、無欠陥シリコン単結晶を少なくともスライスし、スライスされたウェーハを鏡面研磨してシリコンウェーハを準備する。このウェーハ加工工程は特に制限されず、一般的に行われている工程のいずれをも適用できる。特に、スライスの後、面取り、ラッピング、エッチング、鏡面研磨するのが典型的であるがその他の工程としてもよい。また、特に制限されないが、スライスされ、鏡面研磨されたシリコンウェーハとして、直径300mm以上のシリコンウェーハを準備することが好ましい。このような最先端品に用いられる大直径ウェーハであっても、本発明の熱処理工程及び再研磨工程を行うことでLPDが低減された高品質のシリコンウェーハを作製することができる。
本発明の熱処理工程では、鏡面研磨されたシリコンウェーハを、500℃以上600℃以下の温度で、4時間以上6時間以下の時間で熱処理する。このように、重金属、特にCu、Niのシリコン単結晶中における拡散速度が速いことを利用して比較的低温の熱処理工程を行うことで、Cu及びNiを鏡面研磨後のシリコンウェーハの表面近傍に集合させることができる。用いる熱処理炉についても特に制限されず、縦型あるいは横型のバッチ炉を用いれば効率がよい。
本発明の再研磨工程では、熱処理工程後のシリコンウェーハを、研磨量が1.5μm以上となるように再研磨する。このように、再研磨工程によりシリコンウェーハの表面近傍に集合した重金属、特にCu、Niを除去することにより、LPDの発生原因となる重金属を除くことができる。これにより重金属起因の微小なLPDを低減させることができる。ここで、再研磨量は、追加して再研磨する必要のないよう1.5μm以上とする。研磨方法としては、一般的にシリコンウェーハに行われているいずれの研磨方法によることができ、特に制限されない。例えば、研磨剤としてコロイダルシリカを用いたCMPを行うことができる。
また、前記シリコンウェーハの製造方法によって作製されたシリコンウェーハは、無欠陥シリコン単結晶が育成時に重金属で汚染されていたとしても、LPDが極限まで低減され、検査工程及び出荷段階で不良品発生率が低くなり、最先端の半導体素子作製工程に用いられる工程確認用のウェーハや高集積の半導体素子の製造に最適なシリコンウェーハとなる。
直径810mmの石英ルツボに多結晶シリコンを410kg充填し、シリコンの固層/液層境界領域の温度勾配(G)と成長速度(V)を制御することにより直径300mmの無欠陥シリコン単結晶を育成した。この際、比抵抗は10Ω・cmとなるようにボロンをドープし、結晶軸方位は<100>とした。この無欠陥シリコン単結晶にスライス、面取り、ラッピング、エッチング、鏡面研磨を施し鏡面研磨ウェーハを作製した。この鏡面研磨ウェーハを窒素雰囲気中にて熱処理温度500℃、熱処理時間4時間で熱処理をし、その後、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。熱処理、再研磨後のシリコンウェーハのLPDをパーティクルカウンター(KLA Tencor社 モデル名=SP2 検出粒径サイズは0.037μm以上)にて検出した。結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度600℃、熱処理時間4時間で熱処理をし、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度500℃、熱処理時間6時間で熱処理をし、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度500℃、熱処理時間4時間で熱処理をし、再研磨量2.0μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度400℃、熱処理時間4時間で熱処理をし、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度700℃、熱処理時間4時間で熱処理をし、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度500℃、熱処理時間3時間で熱処理をし、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度500℃、熱処理時間8時間で熱処理をし、再研磨量1.5μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
実施例1と同様にして作製した鏡面研磨ウェーハを、熱処理温度500℃、熱処理時間4時間で熱処理をし、再研磨量1.0μmとして再研磨を行ってシリコンウェーハを作製した。LPDの検出結果を表6に示す。
Claims (6)
- CZ法により育成された無欠陥シリコン単結晶からシリコンウェーハを製造する方法であって、
前記無欠陥シリコン単結晶からスライスされ、鏡面研磨されたシリコンウェーハを準備した後に、
前記鏡面研磨されたシリコンウェーハを、500℃以上600℃以下の温度で、4時間以上6時間以下の時間で熱処理する熱処理工程と、
前記熱処理工程後のシリコンウェーハを、研磨量が1.5μm以上となるように再研磨する再研磨工程とを行うことを特徴とするシリコンウェーハの製造方法。
- 前記熱処理工程及び前記再研磨工程を行うことによって、パーティクルカウンターで検出される、粒径サイズ37nm以上120nm以下のLPDが10個/wafer以下の前記シリコンウェーハを製造することを特徴とする請求項1に記載のシリコンウェーハの製造方法。
- 前記スライスされ、鏡面研磨されたシリコンウェーハとして、直径300mm以上のシリコンウェーハを準備することを特徴とする請求項1又は請求項2に記載のシリコンウェーハの製造方法。
- 請求項1乃至請求項3のいずれか1項に記載のシリコンウェーハの製造方法によって作製されたシリコンウェーハ。
- 鏡面研磨されたシリコンウェーハを熱処理して再研磨したシリコンウェーハであって、パーティクルカウンターで検出される、粒径サイズ37nm以上120nm以下のLPDが10個/wafer以下であることを特徴とするシリコンウェーハ。
- 前記シリコンウェーハの直径が300mm以上であることを特徴とする請求項5に記載のシリコンウェーハ。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/122,356 US9337013B2 (en) | 2011-06-20 | 2012-05-14 | Silicon wafer and method for producing the same |
KR1020137033445A KR101905826B1 (ko) | 2011-06-20 | 2012-05-14 | 실리콘 웨이퍼 및 그 제조 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-135891 | 2011-06-20 | ||
JP2011135891A JP5682471B2 (ja) | 2011-06-20 | 2011-06-20 | シリコンウェーハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012176370A1 true WO2012176370A1 (ja) | 2012-12-27 |
Family
ID=47422235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/003121 WO2012176370A1 (ja) | 2011-06-20 | 2012-05-14 | シリコンウェーハ及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9337013B2 (ja) |
JP (1) | JP5682471B2 (ja) |
KR (1) | KR101905826B1 (ja) |
WO (1) | WO2012176370A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104749802A (zh) * | 2013-12-30 | 2015-07-01 | 三星显示有限公司 | 制造显示装置的方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101895817B1 (ko) | 2014-06-02 | 2018-09-07 | 가부시키가이샤 사무코 | 실리콘 웨이퍼 및 그 제조 방법 |
DE102015224933A1 (de) * | 2015-12-11 | 2017-06-14 | Siltronic Ag | Monokristalline Halbleiterscheibe und Verfahren zur Herstellung einer Halbleiterscheibe |
JP6920849B2 (ja) | 2017-03-27 | 2021-08-18 | 株式会社荏原製作所 | 基板処理方法および装置 |
JP2021506718A (ja) | 2017-12-21 | 2021-02-22 | グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. | Llsリング/コアパターンを改善する単結晶シリコンインゴットの処理の方法 |
JP6933187B2 (ja) * | 2018-05-01 | 2021-09-08 | 信越半導体株式会社 | 半導体シリコンウェーハの金属不純物除去方法 |
JP7279682B2 (ja) | 2020-04-17 | 2023-05-23 | 信越半導体株式会社 | シリコンウェーハの評価方法 |
JP7251516B2 (ja) | 2020-04-28 | 2023-04-04 | 信越半導体株式会社 | ウェーハの欠陥領域の判定方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006004983A (ja) * | 2004-06-15 | 2006-01-05 | Shin Etsu Handotai Co Ltd | シリコンウエーハの製造方法及びシリコンウエーハ |
JP2011014645A (ja) * | 2009-06-30 | 2011-01-20 | Covalent Materials Corp | シリコンウエハの熱処理方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2521007B2 (ja) | 1992-06-30 | 1996-07-31 | 九州電子金属株式会社 | シリコン単結晶の製造方法 |
IT1280041B1 (it) | 1993-12-16 | 1997-12-29 | Wacker Chemitronic | Procedimento per il tiraggio di un monocristallo di silicio |
JP3575644B2 (ja) * | 1995-08-28 | 2004-10-13 | 三菱住友シリコン株式会社 | シリコンウェーハの製造方法 |
US20020185053A1 (en) | 2001-05-24 | 2002-12-12 | Lu Fei | Method for calibrating nanotopographic measuring equipment |
JP2009212354A (ja) * | 2008-03-05 | 2009-09-17 | Sumco Corp | シリコン基板の製造方法 |
JP5446160B2 (ja) * | 2008-07-31 | 2014-03-19 | 株式会社Sumco | 再生シリコンウェーハの製造方法 |
WO2010109873A1 (ja) * | 2009-03-25 | 2010-09-30 | 株式会社Sumco | シリコンウェーハおよびその製造方法 |
JP5310848B2 (ja) | 2009-06-05 | 2013-10-09 | 株式会社Sumco | シリコンウェーハの研磨方法及びシリコンウェーハ |
-
2011
- 2011-06-20 JP JP2011135891A patent/JP5682471B2/ja active Active
-
2012
- 2012-05-14 US US14/122,356 patent/US9337013B2/en active Active
- 2012-05-14 KR KR1020137033445A patent/KR101905826B1/ko active IP Right Grant
- 2012-05-14 WO PCT/JP2012/003121 patent/WO2012176370A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006004983A (ja) * | 2004-06-15 | 2006-01-05 | Shin Etsu Handotai Co Ltd | シリコンウエーハの製造方法及びシリコンウエーハ |
JP2011014645A (ja) * | 2009-06-30 | 2011-01-20 | Covalent Materials Corp | シリコンウエハの熱処理方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104749802A (zh) * | 2013-12-30 | 2015-07-01 | 三星显示有限公司 | 制造显示装置的方法 |
US20150187637A1 (en) * | 2013-12-30 | 2015-07-02 | Samsung Display Co., Ltd. | Manufacturing method for display device |
US9362159B2 (en) * | 2013-12-30 | 2016-06-07 | Samsung Display Co., Ltd. | Manufacturing method for display device |
Also Published As
Publication number | Publication date |
---|---|
JP5682471B2 (ja) | 2015-03-11 |
US9337013B2 (en) | 2016-05-10 |
KR101905826B1 (ko) | 2018-10-08 |
JP2013004825A (ja) | 2013-01-07 |
US20140103492A1 (en) | 2014-04-17 |
KR20140046420A (ko) | 2014-04-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5682471B2 (ja) | シリコンウェーハの製造方法 | |
KR100581047B1 (ko) | 실리콘 단결정 웨이퍼의 제조방법 및 실리콘 단결정 웨이퍼 | |
KR101389058B1 (ko) | 실리콘 웨이퍼 및 그 제조방법 | |
KR100573473B1 (ko) | 실리콘 웨이퍼 및 그 제조방법 | |
KR100788988B1 (ko) | 에피텍셜 웨이퍼용 실리콘 단결정 웨이퍼, 에피텍셜웨이퍼 및 이들의 제조방법 그리고 평가방법 | |
KR100854673B1 (ko) | 어닐링된 웨이퍼를 제조하는 방법 | |
KR101272659B1 (ko) | 실리콘 단결정의 제조 방법, 실리콘 단결정 잉곳 및 실리콘 웨이퍼 | |
TWI548785B (zh) | 矽晶圓及其製造方法 | |
JP2002187794A (ja) | シリコンウェーハおよびこれに用いるシリコン単結晶の製造方法 | |
JP6565624B2 (ja) | シリコンウェーハの品質評価方法およびシリコンウェーハの製造方法 | |
JP4854936B2 (ja) | シリコンウエーハの製造方法及びシリコンウエーハ | |
KR100566824B1 (ko) | 실리콘 반도체기판 및 그의 제조방법 | |
JP4196602B2 (ja) | エピタキシャル成長用シリコンウエーハ及びエピタキシャルウエーハ並びにその製造方法 | |
US7311775B2 (en) | Method for heat-treating silicon wafer and silicon wafer | |
TW201929081A (zh) | 處理單晶矽鑄碇以改善雷射光散射環狀/核狀圖案的方法 | |
JP2007073594A (ja) | エピタキシャルシリコンウェーハの製造方法 | |
JP4089137B2 (ja) | シリコン単結晶の製造方法およびエピタキシャルウェーハの製造方法 | |
JP4092993B2 (ja) | 単結晶育成方法 | |
JP5282762B2 (ja) | シリコン単結晶の製造方法 | |
JP2004119446A (ja) | アニールウエーハの製造方法及びアニールウエーハ | |
JP6493105B2 (ja) | エピタキシャルシリコンウェーハ | |
JP5012721B2 (ja) | シリコンエピタキシャルウェーハ | |
JP2004221435A (ja) | 半導体ウエーハの製造方法及び半導体ウエーハ | |
JP2002134513A (ja) | シリコンウェーハの熱処理方法 | |
JP2009035481A (ja) | シリコン単結晶ウエーハ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12803406 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14122356 Country of ref document: US |
|
ENP | Entry into the national phase |
Ref document number: 20137033445 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12803406 Country of ref document: EP Kind code of ref document: A1 |